Xeon + FPGA

Steve Draper
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Posts: 143

Xeon + FPGA Jun 20, 2014 1:18:09 GMT -8

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Post by Steve Draper on Jun 20, 2014 1:18:09 GMT -8

See www.extremetech.com/extreme/184828-intel-unveils-new-xeon-chip-with-integrated-fpga-touts-20x-performance-boost

I particularly noted the 'low latency, coherent' connect, which I think would provide cache coherency for the FPGA to CPU cache (at a guess only L3, but still). This would probably be a very nice propnet platform.

bertrand Administrator Posts: 19	Xeon + FPGA Jun 25, 2014 10:42:25 GMT -8 Quote Select Post Deselect Post Link to Post Member Give Gift Back to Top Post by bertrand on Jun 25, 2014 10:42:25 GMT -8 Each year, we drop a hint at Stanford that students should really try to make it work with an FPGA. So far, we have had no luck, but it indeed looks like a nice platform

Lars Ericson
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Xeon + FPGA Jul 10, 2015 11:17:38 GMT -8 via mobile

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Post by Lars Ericson on Jul 10, 2015 11:17:38 GMT -8

No point at looking at FPGA until you can code OpenCL kernels that do something useful with parallel game simulation. That means moving whole propnet or state machine nextstate logic to GPU plus RNG which is most likely going to be painful in OpenCL.

Post by Steve Draper on Jun 20, 2014 1:18:09 GMT -8

Post by bertrand on Jun 25, 2014 10:42:25 GMT -8

Post by Lars Ericson on Jul 10, 2015 11:17:38 GMT -8

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